1. Field of Invention
The present invention relates to a method of manufacturing a device isolating structure. More particularly, the present invention relates to a method of manufacturing shallow trench isolation.
2. Description of Related Art
An integrated circuit is made from a combination of various device types and isolating structures. Devices are separated from each other by the isolating structures. The most commonly used device isolating structures include shallow trench isolation (STI). FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps in fabricating shallow trench isolation using a conventional method. First, as shown in FIG. 1A, a pad oxide layer 11 is grown over a substrate 10 using, for example, a thermal oxidation method. Then, a chemical vapor deposition (CVD) method is used to form a silicon nitride layer 12 over the pad oxide layer 11. Next, as shown in FIG. 1B, photolithographic and etching techniques are used to pattern the pad oxide layer 11, the silicon nitride layer 12 and the substrate 10. For example, a dry etching method can be used to pattern the pad oxide layer 11 and the silicon nitride layer 12, and to form an opening 13 in the substrate 10 that functions as an STI trench. Thereafter, a liner oxide layer 14 is formed on the bottom and the sidewalls of the opening 13, and then a CVD method is used to deposit oxide into the trench 13 forming an oxide layer 15. Subsequently, as shown in FIG. 1C, the oxide layer 15 is polished using a chemical-mechanical polishing (CMP) method or etch-back method using the silicon nitride layer 12a as an etching or polishing stop layer. Thereafter, the silicon nitride layer 12a is exposed. Finally, as shown in FIG. 1D, the silicon nitride layer 12a is removed to expose the oxide layer 15a. Then, a gate oxide layer 16 is formed over the substrate 10 followed by subsequent processing operations necessary for the fabrication of complete devices.
In the aforementioned method of fabricating shallow trench isolation, a wet etching method is used to remove the pad oxide layer 11a, in which method hydrofluoric acid is used as an etchant for carrying out the etching operation. Since wet etching is an isotropic etching method, oxide layer 15a surface adjacent to the substrate 10 can be easily over-etched due to the corrosiveness of hydrofluoric acid. One consequence of this is that recesses 17 are formed on the surface of the oxide layer 15a adjacent to the substrate 10.
The formation of recesses 17 will lead to the formation of sharp corners 18 at the junction between the oxide layer 15a and the substrate 10. Therefore, when a gate oxide layer 16 is subsequently deposited over the substrate 10 and oxide layer 15a, a thin layer of gate oxide will be formed over the sharp corner areas 18. Consequently, after the gate is formed, if a voltage is applied to the gate terminal, leakage current can flow from the sharp corner areas 18.
Furthermore, when fabrication of the semiconductor device is finished, the recesses formed between the substrate and oxide layer due to over-etching will tend to accumulate electric charges, which can lower the threshold voltage of the device. This will lead to the generation of abnormal sub-threshold current, known also as the "kink effect". Low threshold voltage combined with abnormal sub-threshold current will lower the quality of the device leading to a reduction in product yield, which is highly undesirable.
To reduce leakage current due to sharp corners, conventional methods rely on minimizing the use of wet etching or reducing the wet etching time. Alternatively, an additional layer of material is deposited over the sharp corner area to smooth out the area. However, these methods are not very efficient.
In light of the foregoing, there is a need to provide an improved method of manufacturing shallow trench isolation.